Modern high speed integrated circuit devices incorporate many high speed receiver (i.e. input), transmitter (i.e. output) and bi-directional (i.e. input and/or output) components. These components, which are also called “input-output”, or simply “I-O” components, receive and transmit data at very high bit rates. For example, multiplexers, cross-connects, routers and switches are commonly constructed using integrated circuits incorporating I-O components capable of operating at serial interface speeds of 622.08 Mbit/s or higher. A single integrated circuit device may incorporate hundreds of high speed I-O components. Each high speed I-O component is electrically coupled to a corresponding one of the integrated circuit's I-O pins.
Before a newly fabricated integrated circuit device is shipped to the customer, the device must be tested to verify, that it operates correctly in accordance with the manufacturer's specifications. Many tests are commonly performed. Some tests can be performed at relatively low speeds with the aid of automated test equipment (ATE). For example, a basic continuity test is initially performed to verify that the electrostatic discharge (ESD) diodes coupled to each one of the integrated circuit's I-O pins are present and functioning properly. ESD diode testing requires direct current (DC) access to the integrated circuit's I-O pins. Another example, well known to persons skilled in the art, is so-called JTAG boundary scan testing, which is typically performed at low speeds on the order of about 5 MHz.
Some tests must be performed at the full rated speed of the device in order to verify that the device operates correctly in accordance with the manufacturer's speed specifications for the device. Such “at-speed” testing can exceed the capabilities of all but the most expensive ATE, making at-speed testing with ATE prohibitively expensive. Even if ATE suitable for at-speed testing is available, the ATE must be configured for at-speed testing in a manner which inhibits the ability of the ATE to perform DC or low speed tests without time-consuming reconfiguration of the ATE. At-speed tests can be performed, without ATE, with the aid of alternate data source and capture (observation) equipment. However, such equipment is expensive and, in any event, is limited to use with only a few of the potentially hundreds of I-O pins coupled to the corresponding high speed I-O components which must undergo at-speed testing.
Built-in self-testing (BIST) enables high speed testing of an integrated circuit device with minimal ATE hardware and functionality requirements. In effect, BIST uses the integrated circuit device to test itself. This is accomplished by designing into and fabricating with the device, test circuitry which is specifically adapted for use in post-fabrication testing the device.
Loopback testing is a common BIST at-speed test technique in which a high speed signal output by one of an integrated circuit device's transmitter components is input (“looped back”) to one of the device's receiver components. The device's low speed ports are used to enable and poll the device's BIST functional elements to execute various BIST tests. By executing and observing a loopback BIST test, one may verify that the transmitter and receiver components operate correctly in accordance with the manufacturer's speed specifications for the device.
A major drawback of loopback testing is that an I-O pin which is connected to specialized loopback test circuitry for at-speed testing cannot be simultaneously connected to ATE for DC or low speed testing. Loopback test circuitry must be impedance-matched to the integrated circuit device component being tested. Simultaneous connection of ATE to the device component being tested introduces an impedance mis-match resulting in unwanted signal reflections which interfere with at-speed testing. The prior art has addressed this problem by using relay banks to switch between loopback test circuitry and ATE at each I-O pin. However, relay bank configuration is time consuming and cumbersome due to the large number (potentially hundreds) of high speed I-O pins involved and due to relays' relatively high failure rates.
Another drawback of loopback testing is that an independent pass/fail test result is not necessarily produced for each I-O pin. For example, an unusually resilient transmitter (driver) may offset a defective (insufficiently sensitive) receiver, producing an incorrect test pass result. Conversely, an overly sensitive receiver may offset a defective (insufficiently powerful) transmitter, producing another incorrect test pass result. Transmitter-receiver interdependency errors of this sort can be avoided by using the ATE to measure the transmitter's output drive level independently of the receiver to confirm that the transmitter's output drive level is within acceptable limits. The transmitter's output signal is subsequently adjusted such that the drive amplitude applied to the receiver is sufficiently small to test the receiver's sensitivity independently of any transmitter drive fluctuations (assuming the transmitter's output drive level is found to be within acceptable limits.). However, BIST techniques facilitate control of the transmitter's output drive level only within a limited range, necessitating provision of additional off-chip attenuation to attain the control range required for transmitter-independent receiver testing. Moreover, each transmitter's output drive level must be measured by the ATE to enable the ATE to programmatically attenuate the transmitters' output drive levels for transmitter-independent receiver testing. As previously explained, any I-O pin which is connected to specialized loopback test circuitry for at-speed testing cannot be simultaneously connected to ATE for DC or low speed testing such as transmitter output drive level adjustment.
This invention provides a high-bandwidth, fixed attenuation loopback path facilitating at-speed BIST of integrated circuit devices incorporating hundreds of high speed I-O components while providing DC test access to the ATE for continuity, DC levels measurement and low speed functional testing.